1. Field of the Invention
The present invention relates to a nonbiased bistable optical device and a method for fabricating the same, and in more particular to a symmetric self electro-optic effect device (hereinafter, referred to as "S-SEED") having optical bistablity when an externally applied voltage is not supplied, and being capable of functioning as an optical logic device.
2. Description of the Prior Art
Optical bistablity is to be a principal character necessary for implementing a parallel optical-signal processing system, an optical exchange, an optical computer or the like, and some optical bistable devices using optical bistablity has been known in the art. One of them is an S-SEED in which two PIN diode SEED's are connected in series and each of the SEED's has a multiple quantum well structure in an intrinsic region thereof. This S-SEED structure is disclosed in the publication of U.S. Pat. No. 4,546,244 entitled "NONLINEAR AND BISTABLE OPTICAL DEVICE" granted Oct. 8, 1985 to Darvid A. B. Miller et al. The publication describes an S-SEED structure having a multiple quantum well (hereinafter, referred to as "MQW") structure, wherein a photocurrent is produced by an optical beam absorbed in the MQW thereof and a voltage responsive to the photocurrent is applied to the MQW, so that an optical absorbance of the MQW is changed. The S-SEED has advantageously a relatively low switching energy and can be easily implemented in two-dimensional array using a conventional fabrication process of compound semiconductor so as to make easy parallel optical-signal processing.
FIG. 1 is a cross-sectional view of a conventional S-SEED, and FIGS. 2 and 3 are a plane view and a diagram of an equivalent circuit, respectively.
Referring to FIGS. 2 and 3, the same components as those in FIG. 1 are indicated by the same reference numerals. Reference numeral 7 indicates interface between mesa-etched portions of PIN diodes and reference numeral 8 represents interface portions etched to electrically isolate elements.
As shown in FIG. 3, the conventional S-SEED is provided with two PIN diode SEED's D1 and D2 which are connected in series. When the S-SEED is supplied with a reverse voltage VAP, it has optical bistablity because one SEED of the two SEED's serves as a load for the other. The reverse voltage VAP is applied to a metal pad 5, as shown in FIGS. 1 and 2. In FIG. 1, reference numerals 1 and 2 indicate n-ohmic metal and p-ohmic metal, respectively. The n-ohmic metal and p-ohmic metal between two PIN diodes are electrically connected by a metal interconnection 4. Similar to, the other ohmic metal is electrically connected to the metal pad 5 through another metal interconnection 4. The S-SEED is supplied with an externally applied voltage through the metal pad 5.
As shown in FIG. 1, the two PIN diodes are electrically isolated with each other by etching an undoped quarter-wavelength reflector stack 11 on a semi-insulating substrate 10. Next, an insulating layer 3 of SiN.sub.x or SiO.sub.2 is formed thereon so as to prevent the S-SEED from electrical crosstalk and surface oxidation. The optical beam is introduced to the PIN diode through an optical window 6.
Hereinafter, a method for fabricating the above described S-SEED will be described with reference to FIGS. 1 and 2.
Referring to FIG. 1, on a semi-insulating substrate 10 is sequentially formed an undoped quarter-wavelength reflector 11, an n type layer, an intrinsic MQW and a p type layer. After formation of the p type layer, a well-known etching process is performed in a vertical direction so as to achieve electrical isolation of PIN diodes. An n-ohmic metal 1 is provided for ohmic contact with the n type layer and then an insulating layer 3 is deposited thereon to prevent the device from electrical crosstalk and surface oxidation. Next, the insulating layer 3 is selectively removed to form an optical input/output window 6 on the p type layer, a p-ohmic metal 2 is deposited on the p type layer and a metal interconnection layer 4 is coated to achieve an electrical interconnection. Finally, a thick metal pad 5 is provided on the insulating layer 3 for wire-bonding.
In the S-SEED fabricated by the above method, when two PIN diodes connected in series are supplied with a reverse voltage VAP, one diode of the two PIN diodes serves as a load for the other. Then, a photocurrent occurring due to the reverse voltage has nonlinearity according to nonlinear absorbance of the MQW therein, and thus a voltage across each of the PIN diodes is not to be VAP/2 [V].
FIG. 17 shows a two-dimensional array of 4 by 8 using a conventional S-SEED. It can be seen from FIG. 17 that the array has a similar structure even if a two-dimensional array becomes larger. As shown in FIG. 17, since each S-SEED of the two-dimensional array has to be supplied with a reverse voltage, a metal line has to be inevitably located between S-SEED's and a metal pad is required for wire-bonding.
In FIG. 18, an equivalent circuit of the two-dimensional array of FIG. 17 is shown and all of S-SEED's are electrically connected. In this connection, if only one S-SEED is short-circuited with another S-SEED, the array can not be used for an integrated circuit because a reverse voltage can be applied thereto. Also, if S-SEED's in the array increase in number, a metal line for electrical connection with the p type layer is liable to be in contact with a metal line for electrical connection with the n type layer. In case S-SEED's are arranged in the two-dimensional array as shown in FIG. 17, the array needs to include metal interconnection lines for supplying a reverse voltage and connecting elements, a metal pad for wire-bonding, and a wiring line for applying an external source. Thus, such additionally requiring lines cause inductive coupling between the lines, electromagnetic interference due to an electromagnetic field and crosstalk. Particularly, in case of formation of an S-SEED array, each of SEED's can not be electrically separated from each other because all cathodes of SEED's have to be connected to an input terminal for one external source supply. Accordingly, if S-SEED's in the array increase in number, the above described problems are more and more serious, whereby to be low in yield and integration degree. Since the metal interconnection and wiring lines also serve as parasitic passive elements in SEED or S-SEED circuit, there is a disadvantage in high-speed switching. Therefore, if an optical device is capable of functioning as an optical logic circuit and has optical bistablity under non-bias of voltage, the above mentioned problems occurring in an S-SEED or an S-SEED array due to a reverse voltage can be eliminated.
FIG. 5 shows a load curve of a photocurrent I.sub.p in a conventional S-SEED circuit. In FIG. 5, a horizontal axis of the load curve is a voltage V to be applied to the anode of a first diode D1 as shown in FIG. 4. The solid line and dotted line in the load curve indicate load curves of the first and second diodes D1 and D2, respectively. At operation point A, a voltage V equal to nearly zero [V] is applied to the anode of the first diode D1 and a reverse voltage VAP of VAP-V is applied to the anode of the second diode D2. On the contrary, at operation point B, if a voltage of V=VAP is applied to the anode of the first diode D1, to the anode of the second diode a voltage equal to nearly zero [V], VAP-V=0, is applied. In the S-SEED circuit of FIG. 4, the diodes having the same structure are connected in series, but different voltages from each other can be stably applied to the SEED diodes D1 and D2. Thus, different electric fields from each other are induced to MQW's in intrinsic regions of two SEED diodes, respectively, and thereby the diodes are different in optical absorbance. Due to the different optical absorbance in two SEED diodes, each SEED becomes different in reflectance. Also, due to nonlinear photocurrent produced by absorbed optical light, the S-SEED circuit has positive feedback characteristics. As a result, the S-SEED circuit has optical bistablity to serve as an optical logic device, as shown in FIG. 6.
In FIG. 6, the ordinate R indicates optical reflectance of a SEED and the abscissa Pin indicates intensity of input light. is a range of optical bistablity in an S-SEED, Ron is reflectance at ON-state, Roff is reflectance at OFF-state and is the difference Ron-Roff between the reflectance of ON-state and the reflectance of OFF-state. Such a SEED is a device utilizing quantum confined stark effect (hereinafter, referred to as "QCSE"), wherein QCSE means that a heavy hole exciton absorption peak of MQW is red-shifted in accordance with an induced electric field to nonlinearly reduce absorption coefficient at a fixed operation wavelength of the MQW, and thus photocurrent and reflectance are nonlinearly varied in accordance with optical ON/OFF state. This nonlinear characteristics of MQW allow the SEED to serve as an optical logic device in accordance with the above described principle of the S-SEED circuit.
FIG. 7 shows load curves of the S-SEED circuit, which has SEED's utilizing the QCSE, when an externally applied voltage VAP is set to be zero [V]. As can be seen from FIG. 7, at VAP=0, a cross of two curves, an operating point of the S-SEED is only one point as indicated by "C". Thus, two SEED diodes are constantly supplied with zero voltage, e.g. V=0, even if optical beams are simultaneously introduced to each the SEED's of the S-SEED. Therefore, all of the SEED's keep energy band in thermal equilibrium, as shown in FIG. 8. In the above drawing, since the MQW of intrinsic region is induced with only an electric field responsive to a built-in voltage VBI in the respective PIN diodes and each electric field of the diodes is equal, the S-SEED is unable to have an optical bistablity at VAP=0. This is because a difference c between a conduction band energy in barrier and well layers of the SEED utilizing QCSE and the total thickness d of the MQW of intrinsic region are large and thus an electric field responsive to the built-in voltage VBI of the intrinsic region is low, wherein EC and EV indicate a conduction band energy and a valance band energy, respectively, and EF indicates a Fermi energy.
FIG. 9 shows load curves of the S-SEED circuit in which an intrinsic region is formed of a shallow MQW (hereinafter, referred to as "SMQW"). In FIG. 9, VE indicates a voltage applied to the first diode D1 when operating point of the S-SEED circuit having SMQW is a point E, and VF indicates a voltage applied to the first diode D1 when operating point of the S-SEED circuit having MQW is a point F. FIG. 10 shows an energy band of thermal equilibrium in the S-SEED circuit having the load characteristics of FIG. 9. In FIG. 9, there exist stably operating points E and F, even if VAP=0, and this means that different voltages may be applied to two SEED devices of the S-SEED circuit. As a result, the S-SEED circuit has optical characteristics even when VAP=0. This is, as shown in FIG. 10, because the SMQW is extremely low, or not more than 30 meV, if any, in a conduction band energy offset between well and barrier layers thereof, thereby allowing it to cause a low-field electroabsorption.
FIG. 11 shows an example of a well-known reflection type SEED. With reference to FIG. 11, the reflection type SEED has a lower mirror, a PIN diode with an MQW layer using as an intrinsic region and a non-reflecting layer, which are sequentially formed on a substrate 11. The lower mirror has a plurality of reflecting layers. Each of the reflecting layers comprises a first .lambda./4n reflecting film 12 in which an optical thickness is a high refractive index having a quarter-exciton operation wavelength of the MQW layer, and a second .lambda./4n reflecting film 13 having a relatively low index. The anti-reflecting layer is provided to improve an absorption coefficient of the SEED. The PIN diode has the MQW layer between an n.sup.- layer 14 and a p.sup.- layer 18. In the PIN diode, the n.sup.- layer 14, p.sup.- layer 18, a barrier layer, a buffer layer and the lower mirror other than the MQW layer are formed of material in which absorption is not caused even at any operation wavelength.
FIG. 12 shows a structural example of an asymmetric Fabry-Perot SEED (hereinafter, referred to as "AFP-SEED"), as another example of the reflection type SEED. As shown in FIG. 12, the AFP-SEED has the same construction as that of FIG. 12 except that an upper mirror is formed in place of the non-reflecting layer on the MQW layer. The upper mirror has the same construction as that of the lower mirror. In the AFP-SEED, a thickness L between the lower and upper mirrors is set to be an integer multiple of quarter-operation wavelength.
FIG. 13 shows a refractive index according to the product .alpha.(E).times.D of absorption coefficient .alpha. and a total thickness D of a light absorbing layer when the AFP-SEED with a non-reflecting layer is 0.32 or 0.5 in refractive index Rf of the upper mirror. In FIG. 13, A1 and A2 are values of .alpha.D to meet the impedance-matching condition of an optical signal introduced in the AFP-SEED when Rf are 0.32 and 0.5, respectively. Since .alpha. is determined by the structure of the MQW layer, it is lowered in accordance with increase of an electric field at exciton resonance wavelength of the MQW, as shown in FIG. 14. Therefore, decrease of .alpha. brings about increase of refractive index as shown in FIG. 13 and thus the AFP-SEED meets a normally-off condition that the refractive index is increased in accordance with increase of the electric field. As a result, the AFP-SEED has optical bistablity.
The normally-off conditions of the AFP-SEED is satisfied in the left regions of A1 and A2 to meet the impedance-matching condition of an optical signal introduced in the AFP-SEED as shown in FIG. 13. In FIGS. 15 and 16, a point of A1 is the value of .alpha.D in the AFP-SEED meeting an impedance-matching condition and a point of B1 is the value of the value of .alpha.D in another AFP-SEED meeting an impedance-mismatching condition. It can be seen from FIGS. 15 and 16 that, in the point of A1 to meet the impedance-matching condition, a value of CR (a ratio of a reflectance of ON state to a reflectance of OFF state, or ON/OFF contrast ratio) is extremely high, but .DELTA.R (a difference between the reflectance of ON state and the reflectance of OFF state) is not more than 0.2. Also, in the point of B1 to meet the impedance-mismatching condition, .DELTA.R can be maintained about 0.3 when the value of CR is sufficiently set about 10.
Particularly, since the value of .alpha. is changed only by an internal voltage without an externally applied voltage under nonbias condition, the value of .alpha..sub.on /.alpha..sub.off is not more than 0.35. Thus, .DELTA.R is also lowered relatively. Therefore, it is necessary to maintain a desirable minimum value of CR and maximize .DELTA.R as large as possible.